Low-Complexity Digit-Level Systolic Gaussian Normal Basis Multiplier
Author:
Funder
Ohio RAPIDS
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/8049574/07981358.pdf?arnumber=7981358
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Symmetric And Asymmetric Algorithms for Susceptible Harmful in Wireless Sensor Network on FPGA Platform;2023 9th International Conference on Advanced Computing and Communication Systems (ICACCS);2023-03-17
2. Design of an S-ECIES Cryptoprocessor Using Gaussian Normal Bases Over GF(2 m );IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2021-04
3. Novel Bit-Parallel and Digit-Serial Systolic Finite Field Multipliers Over $GF(2^m)$ Based on Reordered Normal Basis;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-09
4. Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba Algorithm;2018 IEEE 36th International Conference on Computer Design (ICCD);2018-10
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