Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches-Reference-Cited by-同舟云学术

Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches

Published:2022-07 Issue:7 Volume:30 Page:938-951
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Arikan Kerem¹,Palumbo Alessandro²,Cassano Luca³^ORCID,Reviriego Pedro⁴^ORCID,Pontarelli Salvatore⁵,Bianchi Giuseppe⁶^ORCID,Ergin Oguz⁷,Ottavi Marco⁶^ORCID

Affiliation:

1. Department of Electrical and Electronic Engineering, TOBB University of Economics and Technology, Ankara, Turkey

2. Dipartimento di Elettronica, Ingegneria dell’Informazione, Università degli Studi di Roma Tor Vergata, Rome, Italy

3. Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy

4. Departamento de Ingeniería Telemática, Universidad Carlos III de Madrid, Madrid, Spain

5. Dipartimento di Informatica, Università di Roma La Sapienza, Rome, Italy

6. Dipartimento di Elettronica, Ingegneria dell’Informazione, CNIT (Consorzio Nazionale Iteruniversitario per le Telecomunicazioni), Università degli Studi di Roma Tor Vergata, Rome, Italy

7. Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/9809833/09777885.pdf?arnumber=9777885

Reference43 articles.

1. New cache designs for thwarting software cache-based side channel attacks

2. Architectural Support for Containment-based Security

3. Jintide: Utilizing Low-Cost Reconfigurable External Monitors to Substantially Enhance Hardware Security of Large-Scale CPU Clusters

4. InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy

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