A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs

Author:

Zhou BinORCID,Wang Guangsen,Jie Guisheng,Liu Qing,Wang Zhiwei

Funder

National Natural Science Foundation of China

Key Laboratory of Equipment Pre-Research Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 7 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application;Integration;2024-09

2. A Novel Design of High Speed Multiplier Using Hybrid Adder Technique;2024 3rd International Conference for Innovation in Technology (INOCON);2024-03-01

3. FPGA Implementation of a High Speed Efficient Single Precision Floating Point ALU;2023 International Conference on Control, Communication and Computing (ICCC);2023-05-19

4. Floating-Point Number Scalar Product Hardware Implementation for Embedded Systems;2023 17th International Conference on the Experience of Designing and Application of CAD Systems (CADSM);2023-02-22

5. Design and Analysis of Posit Quire Processing Engine for Neural Network Applications;2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID);2023-01

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