A 10T Soft-Error-Immune SRAM With Multi-Node Upset Recovery for Low-Power Space Applications-Reference-Cited by-同舟云学术

A 10T Soft-Error-Immune SRAM With Multi-Node Upset Recovery for Low-Power Space Applications

Published:2022-03 Issue:1 Volume:22 Page:85-88
ISSN:1530-4388
Container-title:IEEE Transactions on Device and Materials Reliability
language:
Short-container-title:IEEE Trans. Device Mater. Relib.

Author:

Pal Soumitra¹^ORCID,Sahay Shubham²,Ki Wing-Hung¹,Tsui Chi-Ying¹

Affiliation:

1. Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong

2. Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, India

Funder

Hong Kong Research Grants Council Areas of Excellence

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Safety, Risk, Reliability and Quality,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/7298/9730817/09698116.pdf?arnumber=9698116

Reference11 articles.

1. Quadruple Cross-Coupled Latch-Based 10T and 12T SRAM Bit-Cell Designs for Highly Reliable Terrestrial Applications

2. A Soft Error Tolerant 10T SRAM Bit-Cell With Differential Read Capability

3. Soft-error-aware read-stability-enhanced low-power 12T SRAM with multi-node upset recoverability for aerospace applications;pal;IEEE Trans Circuits Syst I Reg Papers,0

4. Upset hardened memory design for submicron CMOS technology

5. Analysis and Design of Nanoscale CMOS Storage Elements for Single-Event Hardening With Multiple-Node Upset

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