40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate-Reference-Cited by-同舟云学术

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40-nm 2×VDD Digital Output Buffer Design With DDR4-Compliant Slew Rate

Published:2018-10 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
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Author:

Wang Chua-Chin,Hou Zong-You,Huang Ssu-Wei

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8596720/8605562/08605678.pdf?arnumber=8605678

Cited by 11 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. 2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues;Integration;2024-09

2. GA-Optimized 6.0-Gbps DDR5 SDRAM I/O Buffer Design for 16-nm FinFET CMOS Process;2024 IEEE 6th International Conference on AI Circuits and Systems (AICAS);2024-04-22

3. A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

4. A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19

5. A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process;Integration;2023-05

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