A novel design of a memristor-based look-up table (LUT) for FPGA
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/7021138/7032694/07032878.pdf?arnumber=7032878
Cited by 18 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits;Applied Reconfigurable Computing. Architectures, Tools, and Applications;2023
2. MESO-LUT: A design approach of look up tables based on MESO devices;Microelectronics Journal;2022-08
3. Memristor-based Pass Gate Targeting FPGA Look-Up Table;2021 International Conference on Electronics, Information, and Communication (ICEIC);2021-01-31
4. Heterogeneous FPGA Architecture using Threshold Logic Gates for Improved Area, Power, and Performance;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2021
5. A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies;IEEE Access;2021
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