Memristor-based Pass Gate Targeting FPGA Look-Up Table-Reference-Cited by-同舟云学术

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Memristor-based Pass Gate Targeting FPGA Look-Up Table

Published:2021-01-31 Issue: Volume: Page:
ISSN:
Container-title:2021 International Conference on Electronics, Information, and Communication (ICEIC)
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Author:

Dao Nguyen Cong,Koch Dirk

Funder

EPSRC

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9369688/9369708/09369751.pdf?arnumber=9369751

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Performance Analysis of Memristor and IMPLY Adder based 64-bit Vedic Multiplier and CAM Memory with Gbps throughput on FPGA;WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL;2022-09-01

2. MESO-LUT: A design approach of look up tables based on MESO devices;Microelectronics Journal;2022-08

3. Memristor based full subtractor;2022 International Conference on Communication, Computing and Internet of Things (IC3IoT);2022-03-10

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