Memristor based full subtractor-Reference-Cited by-同舟云学术

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Memristor based full subtractor

Published:2022-03-10 Issue: Volume: Page:
ISSN:
Container-title:2022 International Conference on Communication, Computing and Internet of Things (IC3IoT)
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Author:

Nissi Vesapaga Grace¹,Musala Sarada¹,J Veerayya²

Affiliation:

1. Vignan's Foundation for Science Technology and Research,Electronics and Communication Engineering,Vadlamudi,Andhra Pradesh,India,522213

2. Vignan's Lara Institute of Technology & Science,Electronics and Communication Engineering,Vadlamudi,A.P,India,522213

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9767722/9767723/09767971.pdf?arnumber=9767971

Reference12 articles.

1. Memristor-Based Logic Gate Circuit

2. LOW POWER MEMRISTOR BASED SHIFT REGION DESIGN;sasi;27th IEEE International Conference on Electronics Circuits and Systems (ICECS) Conference paper,0

3. Memristor circuits and systems for future computing and bio-inspired information processing

4. Design of CMOS full subtractor using 10T for object detection application

5. Device engineering and CMOS integration of nanoscale memristors

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Reconfigurable Stateful Logic Circuit With Cu/CuI/Pt Memristors for In-Memory Computing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-05

2. CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications;Electronics;2023-03-31

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