A Scalable High Throughput Firewall in FPGA
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx5/4724876/4724877/04724888.pdf?arnumber=4724888
Cited by 22 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A high-performance energy efficient packet classification design on FPGA;i-manager's Journal on Communication Engineering and Systems;2023
2. Multibillion packet lookup for next generation networks;Computers & Electrical Engineering;2020-06
3. A Survey on FPGA Support for the Feasible Execution of Virtualized Network Functions;IEEE Communications Surveys & Tutorials;2020
4. A Novel Parallel Approach for Disjoint Rule Generation and Optimization (DRGO) in Reconfigurable Firewall Using FPGA;National Academy Science Letters;2019-12-17
5. Integrated Packet Classification to Support Multiple Security Policies for Robust and Low Delay V2X Services;Mobile Information Systems;2018-11-01
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