A Novel Parallel Approach for Disjoint Rule Generation and Optimization (DRGO) in Reconfigurable Firewall Using FPGA
Author:
Publisher
Springer Science and Business Media LLC
Subject
Engineering (miscellaneous)
Link
http://link.springer.com/content/pdf/10.1007/s40009-019-00862-6.pdf
Reference8 articles.
1. Prajapati GS, Khare N (2012) A framework of an internet firewall for IPv6 using FPGA. Int J Comput Appl 50(21):22–24
2. Wicaksana A, Sasongko A (2011) Fast and reconfigurable packet classification engine in FPGA-based firewall. In: IEEE international conference on electrical engineering and informatics
3. Jedhe G, Ramamoorthy A, Varghese K (2008) A scalable high throughput firewall in FPGA. In: IEEE international symposium on field-programmable custom computing machines
4. Jiang W, Prasanna VK (2009) A FPGA-based parallel architecture for scalable high-speed packet classification. In: IEEE international conference on application-specific systems, architectures and processors
5. Song H, Lockwood JW (2005) Efficient packet classification for network intrusion detection using FPGA. In: Proceedings of ACM/SINDA 13th international symposium on FPGA, pp 238–245
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1. A Highly Configurable Packet Sniffer Based on Field-Programmable Gate Arrays for Network Security Applications;Electronics;2023-10-25
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