A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor-Reference-Cited by-同舟云学术

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A 430-MS/s 7-b Asynchronous SAR ADC With a 40 fF Input Sampling Capacitor

Published:2022-10-19 Issue: Volume: Page:
ISSN:
Container-title:2022 19th International SoC Design Conference (ISOCC)
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Author:

Kim Hyoung-Jung¹,Lee Jae-Hyuk¹,Lim Jae-Geun¹,BOO Jun-Ho¹,Kim Ho-Jin¹,Park Seong-Bo¹,Choi Youngdon²,Choi Jung-Hwan²,Ahn Gil-Cho¹

Affiliation:

1. Sogang University,Department of Electronic Engineering,Seoul,Korea

2. Samsung Electronics,Hwasung,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10031262/10031265/10031358.pdf?arnumber=10031358

Reference6 articles.

1. A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC

2. A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC

3. A Two-Way Interleaved 7-b 2.4-GS/s1-Then-2 b/Cycle SAR ADC With Background Offset Calibration;chan;JSSC,2018

4. A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration

5. 22.3 A 20GHz-BW 6b 10GS/s 32mW time-interleaved SAR ADC with Master T&H in 28nm UTBB FDSOI technology

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