Investigation on ESD Robustness of 20-V GGNMOS and GDPMOS in 4H-SiC Process with 100-ns TLP Pulse
Author:
Affiliation:
1. Institute of Electronics, National Yang Ming Chiao Tung University,Hsinchu,Taiwan
Funder
National Science and Technology Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10382185/10382163/10382191.pdf?arnumber=10382191
Reference8 articles.
1. Design and Characterization of the Junction Isolation Structure for Monolithic Integration of Planar CMOS and Vertical Power MOSFET on 4H-SiC up to 300 °C
2. First Integration of 10-V CMOS Logic Circuit, 20-V Gate Driver, and 600-V VDMOSFET on a 4H-SiC Single Chip
3. Tranmission line pulsing techniques for circuit modeling of ESD phenomena;Maloney
4. Investigation of ESD Protection in SiC BCD Process
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