Ka-Band Low Loss and High Power SPDT Switch with Stacked-FET Topology
Author:
Affiliation:
1. University of Electronic Science and Technology of China,School of Physics,Chengdu,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9845797/9845820/09846188.pdf?arnumber=9846188
Reference9 articles.
1. Ka-Band Low-Loss and High-Isolation 0.13 μm CMOS SPST/SPDT Switches Using High Substrate Resistance
2. 100 watt HMIC asymmetric PIN diode switch;rozbicki;2010 Asia-pacific Microwave Conference,2010
3. Single-Pole Double-Throw Switch Using Stacked-FET Configuration at Millimeter Wave Frequencies
4. A K-Band High Power and High Isolation Stacked-FET Single Pole Double Throw MMIC Switch Using Resonating Capacitor
5. A Ka-Band Low-Loss SPDT Switch with Gate Floating Technique
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of DC-18 GHz high-isolation and high-power SPDT;Second International Conference on Electrical, Electronics, and Information Engineering (EEIE 2023);2024-01-15
2. Millimeter-Wave single-pole-double-throw switch design with Stacked-FET topology using network cascading analysis;AEU - International Journal of Electronics and Communications;2023-12
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