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Buffer Reduction Via N-Phase Clocking in Adiabatic Quantum-Flux-Parametron Benchmark Circuits

  • Published:2021-09 Issue:6 Volume:31 Page:1-8
  • ISSN:1051-8223
  • Container-title:IEEE Transactions on Applied Superconductivity
  • language:
  • Short-container-title:IEEE Trans. Appl. Supercond.

Author:

Saito RoORCID,Ayala Christopher L.ORCID,Yoshikawa NobuyukiORCID

Funder

Office of the Directory of National Intelligence

Intelligence Advanced Research Projects Activity

Army Research Office

Grant-in-Aid for Scientific Research

Grant-in-Aid for Early-Career Scientists

Japan Society for the Promotion of Science

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Impact of Sequential Design on the Cost of Adiabatic Quantum-Flux Parametron Circuits;IEEE Transactions on Applied Superconductivity;2023-11

2. Results From the ColdFlux Superconductor Integrated Circuit Design Tool Project;IEEE Transactions on Applied Superconductivity;2023-11

3. SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

4. A Full-Custom Design Flow and a Top-Down RTL-to-GDS Flow for Adiabatic Quantum-Flux-Parametron Logic Using a Commercial EDA Design Suite;IEEE Transactions on Applied Superconductivity;2023-08

5. Beyond local optimality of buffer and splitter insertion for AQFP circuits;Proceedings of the 59th ACM/IEEE Design Automation Conference;2022-07-10
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