Author:
Zhou Yanling,Yan Yunyao,Yan Wei
Cited by
5 articles.
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1. Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans;Engineering, Technology & Applied Science Research;2023-12-05
2. Methodology for Timing Closure in VLSI Physical Design containing high clock to Q Memory Delay;2023 IEEE Silchar Subsection Conference (SILCON);2023-11-03
3. Physical Implementation of Multi Power Domain SoC Design;2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT);2023-07-06
4. Digital Backend Optimization Techniques for Post-Route and Sign-Off Challenges in ASIC Design;Proceedings of Second International Conference on Computational Electronics for Wireless Communications;2023
5. A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs;Proceedings of the 2021 International Symposium on Physical Design;2021-03-21