A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs
Author:
Affiliation:
1. University of Utah, Salt Lake City, UT, USA
Funder
Air Force Research Laboratory (AFRL) and Defense Advanced Research Projects Agency (DARPA)
Publisher
ACM
Link
https://dl.acm.org/doi/pdf/10.1145/3439706.3447047
Reference20 articles.
1. Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
2. Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology
3. Design flow for embedded FPGAs based on a flexible architecture template
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