A Fully Integrated 26.5 dBm CMOS Power Amplifier for IEEE 802.11a WLAN Standard with on-chip "power inductors"
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/4014788/4014789/04015322.pdf?arnumber=4015322
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 5.3-GHz 30.1-dBm Fully Integrated CMOS Power Amplifier With High-Power Built-In Linearizer;IEEE Microwave and Wireless Technology Letters;2023-04
2. Performance of cascode Class‐EF −1 PA with built‐in techniques for UWB radar toward monitoring of patient actions;IET Circuits, Devices & Systems;2020-01-31
3. Design of a 5.2-GHz CMOS Power Amplifier Using TF-Based 2-Stage Dual-Radial Power Splitting/Combining Architecture;IEEE Transactions on Circuits and Systems I: Regular Papers;2019-10
4. Design of a 5.3-GHz 31.3-dBm Fully Integrated CMOS Power Amplifier Using Folded Splitting and Combining Architecture;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2019-07
5. 5.3 GHz 42% PAE class‐E power amplifier with 532 mW/mm 2 power area density in 180 nm CMOS process;Electronics Letters;2016-07
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