60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm2 Nb process
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6598362/6604250/06604272.pdf?arnumber=6604272
Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation;IEICE Transactions on Electronics;2016
2. 50 GHz Demonstration of an Integer-Type Butterfly Processing Circuit for an FFT Processor Using the 10 kA/cm2 Nb Process;IEICE Transactions on Electronics;2015
3. Energy efficiency of adiabatic superconductor logic;Superconductor Science and Technology;2014-11-26
4. Recent Progress of Superconducting Integrated Circuit Technologies Challenging the Limits in Low Power Consumption;IEEJ Transactions on Fundamentals and Materials;2014
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