High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation
Author:
Affiliation:
1. Graduate School of Engineering, Nagoya University
2. Graduate School of Informatics, Kyoto University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E99.C/6/E99.C_703/_pdf
Reference14 articles.
1. [1] K.K. Likharev and V.K. Semenov, “RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems,” IEEE Trans. Appl. Supercond., vol.1, no.1, pp.3-28, March 1991.
2. [2] N. Takagi, K. Murakami, A. Fujimaki, N. Yoshikawa, K. Inoue, and H. Honda, “Proposal of a desk-side supercomputer with reconfigurable data-paths using rapid single-flux-quantum circuits,” IEICE Trans. Electron., vol.E91-C, no.3, pp.350-355, March 2008.
3. [3] T. Kato, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, and S. Nagasawa, “60-GHz demonstration of an SFQ half-precision bit-serial floating-point adder using 10 kA/cm2 Nb process,” Proc. of 2013 IEEE Superconductive Electronics Conference (ISEC2013), Cambridge, USA, no.PA8, pp.1-3, July 2013.
4. [4] X. Peng, Y. Yamanashi, N. Yoshikawa, A. Fujimaki, N. Takagi, K. Takagi, and M. Hidaka, “Design and high-speed demonstration of single-flux-quantum bit-serial floating-point multipliers using a 10 kA/cm2 Nb Process,” IEICE Trans. Electron., vol.E97-C, no.3, pp.188-193, March 2014.
5. [5] M. Tanaka, K. Obata, K. Takagi, N. Takagi, A. Fujimaki, and N. Yoshikawa, “A high-throughput single-flux quantum floating-point serial divider using the signed-digit representation,” IEEE Trans. Appl. Supercond., vol.19, no.3, pp.653-656, June 2009.
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