Design of AXI bus interface modules on FPGA

Author:

Bhaktavatchalu Ramesh,Rekha B. Sasi,Divya G. Ananta,Jyothi V. Usha Sai

Publisher

IEEE

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. High Performance and Low Power Axi-Lite 4 Master Controller Using System Verilog;2024 2nd International Conference on Artificial Intelligence and Machine Learning Applications Theme: Healthcare and Internet of Things (AIMLA);2024-03-15

2. High performance and low area interconnect structure based on AXI;Workshop on Electronics Communication Engineering (WECE 2023);2024-01-16

3. GPU@SAT, the AI enabling ecosystem for on-board satellite applications;2023 European Data Handling & Data Processing Conference (EDHPC);2023-10-02

4. A Hardware-based SoC Monitoring In-life Solution for Automotive Industry;2022 IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events (PerCom Workshops);2022-03-21

5. Efficient Support of AXI4 Transaction Ordering Requirements in Many-Core Architecture;IEEE Access;2020

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