A 28nm 11.2TOPS/W Hardware-Utilization-Aware Neural-Network Accelerator with Dynamic Dataflow
Author:
Affiliation:
1. National Taiwan University,Taipei,Taiwan
2. Delta Electronics,Taipei,Taiwan
3. Taiwan Semiconductor Research Institute,Hsinchu,Taiwan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067774.pdf?arnumber=10067774
Reference6 articles.
1. A Multi-Mode 8K-MAC HW-Utilization-Aware Neural Processing Unit with a Unified Multi-Precision Datapath in 4nm Flagship Mobile SoC
2. 9.5 A 6K-MAC Feature-Map-Sparsity-Aware Neural Processing Unit in 5nm Flagship Mobile SoC
3. MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings
4. DepFiN: A 12nm, 3.8TOPs depth-first CNN processor for high res. image processing
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