10.2 A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness
Author:
Affiliation:
1. University of Macau,Macau,China
2. Xidian University,Xi'an,China
Funder
Macau FDCT
University of Macau
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10067248/10067251/10067822.pdf?arnumber=10067822
Reference5 articles.
1. A 12-ENOB Second-Order Noise Shaping SAR ADC with PVT-insensitive Voltage-Time-Voltage Converter
2. 16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation
3. 3.5 A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques
4. A 4-GS/s 39.9-dB SNDR 11.7-mW Hybrid Voltage-Time Two-Step ADC With Feedforward Ring Oscillator-Based TDCs
5. 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1 dB SNDR variation;huang;ISSCC,2017
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2. 22.3 A 76mW 40GS/s 7b Time-Interleaved Hybrid Voltage/Time-Domain ADC with Common-Mode Input Tracking;2024 IEEE International Solid-State Circuits Conference (ISSCC);2024-02-18
3. A 7-b 76-mW 40-GS/s Hybrid Voltage/Time-Domain ADC With Common-Mode Input Tracking;IEEE Solid-State Circuits Letters;2024
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