A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS-Reference-Cited by-同舟云学术

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A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS

Published:2010-07 Issue: Volume: Page:
ISSN:
Container-title:2010 IEEE Computer Society Annual Symposium on VLSI
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Author:

Leshner Samuel,Berezowski Krzysztof,Yao Xiaoyin,Chalivendra Gayathri,Patel Saurabh,Vrudhula Sarma

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5570021/5571793/05572773.pdf?arnumber=5572773

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Implementation and Applications of a Ternary Threshold Logic Gate;Circuits, Systems, and Signal Processing;2023-09-25

2. One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory;ACM Journal on Emerging Technologies in Computing Systems;2017-03-10

3. Delay Analysis for Current Mode Threshold Logic Gate Designs;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-03

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