One-Step Sneak-Path Free Read Scheme for Resistive Crossbar Memory

Abstract

A one-step sneak-path free read scheme for resistive crossbar memory is proposed in this article. During read operation, it configures the crossbar array into a four-terminal resistance network, which is composed of the selected cell and three other resistors corresponding to unselected cells that contribute to the sneak-path. Two sensing voltages with equal potential are applied to three terminals of the network. One is for sensing the resistance of the selected cell; the other is for creating zero-voltage drop across one of the three resistors, which connects the sneak-path to the selected cell. This effectively suppresses the current injected by the sneak-path to the selected cell-sensing loop. This work also proposes a cost-effective data-encoding circuit that guarantees that at least half of the memory cells are in a high-resistance state, which further minimizes sneak-path current. The impact of key design parameters, such as sensing voltage, switch on-resistance, and the ratio of memory cell resistances in different states, as well as nonideal effects are investigated. Equations for estimating the maximum array size to share a single read circuit are derived. The effectiveness of the proposed design has been validated via circuit simulations. Impacts of the word-/bit-line resistance are also analyzed.