Tunnel FET based Standard Logic Cell Implementation: A Circuit Perspective
Author:
Affiliation:
1. NIT Rourkela,Department of ECE,Rourkela,India
2. Kalyani Govt. Engineering College,Department of ECE,Kolkata,India
3. KIIT Deemed to be University,School of Electronics Engineering,Bhubaneswar,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10127221/10127228/10127359.pdf?arnumber=10127359
Reference24 articles.
1. TFET Inverters With n-/p-Devices on the Same Technology Platform for Low-Voltage/Low-Power Applications
2. Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance
3. Investigation of backgate-biasing effect for ultra-thin-body III-V heterojunction tunnel FET;fan;IEEE Trans Electron Devices,2015
4. Tunnel FET-based pass-transistor logic for ultra-low-power applications
5. Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices
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