1. Towards Resilient Quasi Delay Insensitive Conditional Control Elements;2023 26th Euromicro Conference on Digital System Design (DSD);2023-09-06
2. ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic;2023 28th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC);2023-07-16
3. Towards Resilient QDI Pipeline Implementations;2022 25th Euromicro Conference on Digital System Design (DSD);2022-08
4. A Concurrent Testing Scheme for Muller Circuits Using Reduced Ordered Binary Decision Diagram;2022 IEEE Region 10 Symposium (TENSYMP);2022-07-01
5. Input/Output-Interlocking for Fault Mitigation in QDI Pipelines;2021 Austrochip Workshop on Microelectronics (Austrochip);2021-10-14