A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme
Author:
Funder
Ministry of Science and Technology, Taiwan
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8919/8972641/08755503.pdf?arnumber=8755503
Cited by 23 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 12-bit 50MS/s SAR ADC with non-binary split capacitive DAC in 40nm CMOS;IEICE Electronics Express;2024-08-25
2. An 800 kS/s 1.83 fJ/conv. 12b ADC via Voltage Successive Approximation and Gated Cyclic Vernier Time Digitization;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. A Novel Bootstrapped CMOS Switch with Minimized Sampling and Holding Error Using Sampling Window Error Analysis;Journal of Circuits, Systems and Computers;2024-04-25
4. A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor;Electronics;2024-01-19
5. An Energy-Efficient and Area-Saving Capacitor Switching Scheme for SAR ADCs;2023 IEEE 17th International Conference on Anti-counterfeiting, Security, and Identification (ASID);2023-12-01
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