A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC-Reference-Cited by-同舟云学术

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A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC

Published:2018-11 Issue:11 Volume:65 Page:3639-3650
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Zhang Hongshuai^ORCID,Zhang Hong^ORCID,Sun Quan,Li Jijun,Liu Xipeng,Zhang Ruizhi

Funder

National Natural Science Foundation of China

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/8485519/08439071.pdf?arnumber=8439071

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation;Sensors;2024-05-21

2. A 0.5 V 10-bit SAR ADC with offset calibrated time-domain comparator;AEU - International Journal of Electronics and Communications;2024-05

3. Design of 12-bit 4 MS/s SAR ADC based on 40nm process;Third International Conference on Computer Technology, Information Engineering, and Electron Materials (CTIEEM 2023);2024-04-01

4. A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications;Micromachines;2023-12-27

5. A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications;Micromachines;2023-12-15

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