A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration-Reference-Cited by-同舟云学术

A 13-Bit 260MS/s Power-Efficient Pipeline ADC Using a Current-Reuse Technique and Interstage Gain and Nonlinearity Errors Calibration

Published:2019-09 Issue:9 Volume:66 Page:3373-3383
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Zhou Dadian^ORCID,Briseno-Vidrios Carlos^ORCID,Jiang Junning^ORCID,Park Chulhyun^ORCID,Liu Qiyuan^ORCID,Soenen Eric G.,Kinyua Martin,Silva-Martinez Jose^ORCID

Funder

National Science Foundation

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

https://ieeexplore.ieee.org/ielaam/8919/8818466/8760523-aam.pdf

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