A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS-Reference-Cited by-同舟云学术

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A Systematic Study of ESD Protection Co-Design With High-Speed and High-Frequency ICs in 28 nm CMOS

Published:2016-10 Issue:10 Volume:63 Page:1746-1757
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Lu Fei,Ma Rui,Dong Zongyu,Wang Li,Zhang Chen,Wang Chenkun,Chen Qi,Wang X. Shawn,Zhang Feilong,Li Cheng,Tang He,Cheng Yuhua,Wang Albert

Funder

Deparment of Science & Technology of Sichuan Province

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8919/7577914/07552573.pdf?arnumber=7552573

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2. Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging;Electronics;2024-06-15

3. Enhancing chip performance and reliability by CMOS+X technologies;Applied Physics Reviews;2024-06-01

4. A Novel DTSCR Structure with High Holding Voltage and Enhanced Current Discharge Capability for 28 nm CMOS Technology ESD Protection;Micromachines;2023-12-31

5. On-chip ESD Protection Design Methodologies by CAD Simulation;ACM Transactions on Design Automation of Electronic Systems;2023-11-15

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