A Power-Efficient, F-Band, 6.5-dB NF, Staggered-Tuned, Inverter-Based CMOS LNA for 6G Receivers
Author:
Affiliation:
1. University of California,Department of Electrical and Computer Engineering,Irvine,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10600173/10600174/10600407.pdf?arnumber=10600407
Reference13 articles.
1. A 300-GHz 52-mW CMOS Receiver With On-Chip LO Generation
2. A 115–135-GHz 8PSK Receiver Using Multi-Phase RF-Correlation-Based Direct-Demodulation Method
3. A Study of a Millimeter-Wave Transmitter Architecture Realizing QAM Directly in RF Domain
4. A 140–220-GHz Low-Noise Amplifier With 6-dB Minimum Noise Figure and 80-GHz Bandwidth in 130-nm SiGe BiCMOS
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