Author:
Barman Jayeeta,Kumar Vinay
Cited by
8 articles.
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1. An Approximate Full-Adder to Eliminate Carry Propagation in Lower Significant Stage of a Multi-Digit Adder;2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3);2023-06-08
2. Implementation of Carry Look Ahead Adder with 2-bit Approximate Adder;2023 2nd International Conference on Applied Artificial Intelligence and Computing (ICAAIC);2023-05-04
3. Design of High Performance Parallel Multiplication using FPGA;2022 IEEE International Conference on Current Development in Engineering and Technology (CCET);2022-12-23
4. Low-Power High-Speed Eight-Bit Universal Shift Register Design Using Clock Gating Technique;Advances in Computer and Electrical Engineering;2022-12-16
5. Comparative Analysis of Different Clock Gating Techniques;2020 5th IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE);2020-12-01