Design of High Performance Parallel Multiplication using FPGA

Author:

R Jenila1,C Supraja1,N Dharani1,V Dinesh Kumar1

Affiliation:

1. Institute of Science and Technolgy,Electronics and Communication, Vel Tech Rangarajan Dr Sagunthala R&D,Chennai,India

Publisher

IEEE

Reference21 articles.

1. Comparative study of FFA architectures using different multiplier and adder topologies;paliwal;Microsyst Technol,2019

2. Comparison between various types of adder topologies;kaur;IJCST,2015

3. Low area Energy efficient Carry select Adder at 65nm technology;neelasupraja;ICRAESIT,2015

4. Low-Power and Area-Efficient Carry Select Adder

5. Comparative study on word length reduction and truncation for low power multipliers;de la guiasolaz;Proceedings of the 33rd International Convention MIPRO,2010

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