A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS-Reference-Cited by-同舟云学术

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A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS

Published:2018-06 Issue: Volume: Page:
ISSN:
Container-title:2018 IEEE Symposium on VLSI Circuits
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Author:

Kuan Ting-Kuei,Wu Chin-Yang,Shen Ruei-Pin,Chang Chih-Hsien,Hsieh Kenny,Chen Mark

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8484863/8502213/08502365.pdf?arnumber=8502365

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Benchmark Figure of Merit Extensions for Low Jitter Phase Locked Loops Inspired by New PLL Architectures;IEEE Access;2022

2. A 0.0048mm² 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS;2021 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA);2021-11-24

3. A Fully-Synthesizable Fractional-N Injection-Locked PLL for Digital Clocking with Triangle/Sawtooth Spread-Spectrum Modulation Capability in 5-nm CMOS;IEEE Solid-State Circuits Letters;2020

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