A 25-Gb/s 2.2-W optical transceiver using an analog FE tolerant to power supply noise and redundant data format conversion in 65-nm CMOS
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx5/6235082/6243757/06243812.pdf?arnumber=6243812
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS;IEEE Access;2024
2. A 112-Gb/s —8.2-dBm Sensitivity 4-PAM Linear TIA in 16-nm CMOS With Co-Packaged Photodiodes;IEEE Journal of Solid-State Circuits;2023-03
3. Today’s computing challenges: opportunities for computer hardware design;PeerJ Computer Science;2021-03-30
4. A 0.36 pJ/bit, 0.025 mm ${}^{\text{2}}$ , 12.5 Gb/s Forwarded-Clock Receiver With a Stuck-Free Delay-Locked Loop and a Half-Bit Delay Line in 65-nm CMOS Technology;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-09
5. A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection;IEEE Transactions on Circuits and Systems I: Regular Papers;2015-03
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