A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS-Reference-Cited by-同舟云学术

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A reconfigurable sense amplifier with 3X offset reduction in 28nm FDSOI CMOS

Published:2015-06 Issue: Volume: Page:
ISSN:
Container-title:2015 Symposium on VLSI Circuits (VLSI Circuits)
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Author:

Khayatzadeh Mahmood,Frustaci Fabio,Blaauw David,Sylvester Dennis,Alioto Massimo

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7196579/7231231/07231284.pdf?arnumber=7231284

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM;IEICE Electronics Express;2023-12-25

2. Evaluating Sense Amplifier Performance in SRAM Circuits;2023 3rd International Conference on Technological Advancements in Computational Sciences (ICTACS);2023-11-01

3. Body Biased Sense Amplifier With Auto-Offset Mitigation for Low-Voltage SRAMs;IEEE Transactions on Circuits and Systems I: Regular Papers;2021-08

4. A 0.4µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology;2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID);2021-02

5. Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology;2020 IEEE Nordic Circuits and Systems Conference (NorCAS);2020-10-27

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