A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration

Author:

Chu Jack,Brooks Lane,Lee Hae-Seung

Publisher

IEEE

Cited by 16 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Effective Gain Analysis and Statistic Based Calibration for Ring Amplifier With Robustness to PVT Variation;IEEE Transactions on Circuits and Systems II: Express Briefs;2022-02

2. A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs;IEEE Journal of Solid-State Circuits;2018-11

3. An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS;IEEE Transactions on Circuits and Systems I: Regular Papers;2016-10

4. A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2016-07

5. A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers;IEEE Journal of Solid-State Circuits;2015-12

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