Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier-Reference-Cited by-同舟云学术

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Offset Voltage Analysis and Enable Signal Rise Time Control Based Offset Reduction Technique of Current-Latched Sense Amplifier

Published:2021-01-31 Issue: Volume: Page:
ISSN:
Container-title:2021 International Conference on Electronics, Information, and Communication (ICEIC)
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Author:

Na Taehui

Funder

National Research Foundation of Korea (NRF)

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9369688/9369708/09369783.pdf?arnumber=9369783

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Real‐time bit‐line leakage balance circuit with four‐input low‐offset SA considering threshold voltage for SRAM stability design;International Journal of Circuit Theory and Applications;2024-08-15

2. An Automatic Offset Compensation Sense Amplifier Featuring High Readout Reliability for SRAM;2023 20th International SoC Design Conference (ISOCC);2023-10-25

3. Offset-Canceling Current-Latched Sense Amplifier With Slow Rise Time Control and Reference Voltage Biasing Techniques;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-07

4. An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset;Microelectronics Journal;2022-10

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