Author:
Beerel P.A.,Yun K.Y.,Chou W.C.
Cited by
11 articles.
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1. Literal Decomposition for LUT-Oriented Asynchronous Dual-Rail Logic Synthesis;Journal of Circuits, Systems and Computers;2015-06-17
2. Dual-rail asynchronous logic multi-level implementation;Integration;2014-01
3. Asynchronous sum-of-products logic minimization and orthogonalization;International Journal of Circuit Theory and Applications;2012-11-12
4. Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints;2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools;2010-09
5. Asynchronous two-level logic of reduced cost;2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems;2009