1. Power Efficient Hybrid Low-Power Technique for an SRAM cell;2024 IEEE 4th International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2024-05-17
2. Robust Body Biased Level Shifter;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13
3. An Enhanced Clock Tree Synthesis Methodology for Optimizing Power in Physical Design;2022 IEEE 3rd International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA);2022-12-15
4. Reconfigurable Clock Rate Based Synchronous Binary Counter;2022 IEEE 2nd Mysore Sub Section International Conference (MysuruCon);2022-10-16
5. A Cascode Current Mirror Based 90 mV to 1.8 V Level Shifter with Alleviated Delay;2022 International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics ( DISCOVER);2022-10-14