Future challenges in electronics packaging-Reference-Cited by-同舟云学术

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Future challenges in electronics packaging

Published:1998-03 Issue:2 Volume:14 Page:45-54
ISSN:8755-3996
Container-title:IEEE Circuits and Devices Magazine
language:
Short-container-title:IEEE Circuits Devices Mag.

Author:

Chi Shih Chang ,Oscilowski A.,Bracken R.C.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Instrumentation,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx4/101/14656/00666591.pdf?arnumber=666591

Cited by 59 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Investigating moisture diffusion in Mold Compounds (MCs) for Fan-Out-Wafer-Level-Packaging (FOWLP);2022 IEEE 72nd Electronic Components and Technology Conference (ECTC);2022-05

2. Application of the surface planer process to Cu pillars and wafer support tape for high-coplanarity wafer-level packaging;The International Journal of Advanced Manufacturing Technology;2022-01-07

3. Study on Process Induced out-of-plane deformation for Fan-Out Wafer Level Packaging;2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC);2020-09-15

4. A Multiparameter Numerical Modeling and Simulation of the Dipping Process in Microelectronics Packaging;IEEE Transactions on Industrial Informatics;2019-07

5. A CAD approach for pre-layout optimal PDN design and its post-layout verification;Microprocessors and Microsystems;2019-03

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