Vedic and conventional methods of N × N Binary Multiplication with hardware implementation-Reference-Cited by-同舟云学术

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Vedic and conventional methods of N × N Binary Multiplication with hardware implementation

Published:2015-12 Issue: Volume: Page:
ISSN:
Container-title:2015 International Conference on Smart Sensors and Systems (IC-SSS)
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Author:

Patel Pranav,Shandilya Ashish,Brahmbhatt Nisarg,Raval Kshitij,Deb Dipankar

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7867999/7873582/07873592.pdf?arnumber=7873592

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra;Proceedings of the 13th International Conference on Advances in Information Technology;2023-12-06

2. Design and Implementation of General Hardware Binary Multiplier (2ⁿ x 2ⁿ) Bits;Journal of Physics: Conference Series;2022-08-01

3. Low-Power and Area-Efficient Design of Higher-Order Floating-Point Multipliers Using Vedic Mathematics;Lecture Notes in Electrical Engineering;2019-09-25

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