Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra-Reference-Cited by-同舟云学术

Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra

Published:2023-12-06 Issue: Volume: Page:
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Container-title:Proceedings of the 13th International Conference on Advances in Information Technology
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Author:

Arun Anchit¹^ORCID,Chakraborty Ananya²^ORCID,Dutta Priyanka²^ORCID,Pal Debajyoti³^ORCID,Nag Tridibesh⁴^ORCID,De Debasis⁵^ORCID,Ghosh Sudip¹^ORCID,Rahaman Hafizur²^ORCID

Affiliation:

1. School of VLSI Technology, Indian Institute of Engineering Science and Technology(IIEST), India

2. Indian Institute of Engineering Science and Technology(IIEST), India

3. King Mongkut's University of Technology Thonburi, Thailand

4. Netaji Subhash Engineering College, India

5. Maulana Abul Kalam Azad University of Technology, India

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3628454.3631153

Reference20 articles.

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2. Vedic and conventional methods of N × N Binary Multiplication with hardware implementation

3. Weste , N.H.E. , Harris , D. , Banerjee , A. : CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition, Pearson Education ,pp. 327 - 328 , ( 2006 ). Weste, N.H.E., Harris, D., Banerjee, A.: CMOS VLSI Design, A Circuits and Systems Perspective, Third Edition, Pearson Education,pp. 327-328, (2006).

4. Jagadguru Swami Sr i Bharati Krisna Tirthaji Maharaja, Vedic Mathematics : Sixteen Simple Mathematical Formulae from the Veda , Delhi , 1965 . Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda, Delhi, 1965.

5. Chudasama , A. , Sasamal , T and Yadav , Jyoti. : An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata. computers & Electrical Engineering . vol. 65 . pp. 527 - 542 ( 2018 ). Chudasama, A., Sasamal, T and Yadav, Jyoti.: An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata. computers & Electrical Engineering. vol. 65. pp. 527-542 (2018).