Modeling the Thermal and Power Control Subsystem in HPC Processors
Author:
Affiliation:
1. Università ALMA Mater Studiorum,Bologna,Italy
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9965973/9965785/09966082.pdf?arnumber=9966082
Reference14 articles.
1. RAPL in Action
2. Bias-Compensated Least Squares Identification of Distributed Thermal Models for Many-Core Systems-on-Chip
3. “Zeppelin”: An SoC for Multichip Architectures
4. Power/Performance Controlling Techniques in OpenPOWER
5. An Open-Source Scalable Thermal and Power Controller for HPC Processors
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Modeling and Controlling Many-Core HPC Processors: an Alternative to PID and Moving Average Algorithms;ACM Transactions on Autonomous and Adaptive Systems;2024-09-09
2. ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation;International Journal of Parallel Programming;2024-02-26
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