Accelerating NoC Verification Using a Complete Model and Active Window-Reference-Cited by-同舟云学术

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Accelerating NoC Verification Using a Complete Model and Active Window

Published:2022 Issue: Volume:10 Page:88985-88999
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Das Surajit¹^ORCID,Karfa Chandan²^ORCID,Biswas Santosh³^ORCID

Affiliation:

1. Department of Computer Science and Engineering, GITAM School of Technology, Bengaluru, Karnataka, India

2. Department of Computer Science and Engineering, IIT Guwahati, Guwahati, Assam, India

3. Department of Electrical Engineering and Computer Science, IIT Bhilai, Raipur, Chhattisgarh, India

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/9668973/09858921.pdf?arnumber=9858921

Reference38 articles.

1. Semi-formal functional verification by EFSM traversing via NuSMV

2. Automatic Extraction of Micro-Architectural Models of Communication Fabrics from Register Transfer Level Designs

3. ADVOCAT: Automated Deadlock Verification for On-chip Cache Coherence and Interconnects

4. Verifying Deadlock-Freedom of Communication Fabrics

5. Quick formal modeling of communication fabrics to enable verification

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Improving Functional Coverage of Network-On-Chip Using Differential Evolution;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

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