Enhancement of Convolutional Neural Network Hardware Accelerators Efficiency Using Sparsity Optimization Framework
Author:
Affiliation:
1. School of Electronics Engineering (SENSE), Vellore Institute of Technology, Vellore, Tamil Nadu, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx8/6287639/10380310/10559811.pdf?arnumber=10559811
Reference33 articles.
1. A survey of the recent architectures of deep convolutional neural networks
2. Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey
3. Knowledge Graphs in Manufacturing and Production: A Systematic Literature Review
4. Edge Robotics: Edge-Computing-Accelerated Multirobot Simultaneous Localization and Mapping
5. Survey on Big Data Techniques in Intelligent Transportation System (ITS)
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