Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey-Reference-Cited by-同舟云学术

Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey

Author:

Dhilleswararao Pudi¹^ORCID,Boppu Srinivas¹^ORCID,Manikandan M. Sabarimalai²^ORCID,Cenkeramaddi Linga Reddy³^ORCID

Affiliation:

1. School of Electrical Sciences, Indian Institute of Technology Bhubaneswar, Bhubaneswar, India

2. Department of Electrical Engineering, Indian Institute of Technology Palakkad, Palakkad, India

3. Department of ICT, University of Agder, Grimstad, Norway

Funder

Norges Forskningsr?d

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

Reference230 articles.

4. DLAU: A scalable deep learning accelerator unit on FPGA;wang;IEEE Trans Comput -Aided Design Integr Circuits Syst,2017

5. CuDNN: Efficient primitives for deep learning;chetlur;Arxiv 1410 0759,2014

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