High Current Density Vertical Nanowire TFETs With I₆₀ > 1 <i>μ</i>A/<i>μ</i>m-Reference-Cited by-同舟云学术

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High Current Density Vertical Nanowire TFETs With I₆₀ > 1 μA/μm

Published:2023 Issue: Volume:11 Page:95692-95696
ISSN:2169-3536
Container-title:IEEE Access
language:
Short-container-title:IEEE Access

Author:

Rangasamy Gautham¹^ORCID,Zhu Zhongyunshen¹^ORCID,Wernersson Lars-Erik¹^ORCID

Affiliation:

1. Department of Electrical and Information Technology, Lund University, Lund, Sweden

Funder

Swedish Research Council

European Union H2020 Program SEQUENCE

European Research Council through the Dynamic Properties of Ferroelectric III–V MOSFETs

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/6287639/10005208/10234407.pdf?arnumber=10234407

Reference28 articles.

1. Thickness-controlled black phosphorus tunnel field-effect transistor for low-power switches

2. A hybrid III–V tunnel FET and MOSFET technology platform integrated on silicon

3. Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si

4. InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors

5. Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cutting-edge vertical tunnel FETs: GaSb/InSb heterojunction source-all-around tunnel FET with I60 of 2.73×10⁻⁴ A/μm and Sub-10 mV/dec SS;Micro and Nanostructures;2024-10

2. III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance;Semiconductor Science and Technology;2024-08-07

3. A Reconfigurable Ferroelectric Transistor as An Ultra‐Scaled Cell for Low‐Power In‐Memory Data Processing;Advanced Electronic Materials;2024-08-05

4. A complementary ternary inverter based on the line tunneling field effect transistors;Microelectronics Journal;2024-03

5. Optimizing InGaAs/GaAsSb Staggered Bandgap U-Gate Line TFET With p⁺-Pocket Implant and Negative Capacitance for Enhanced Performance;IEEE Transactions on Nanotechnology;2024

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