SEC-BADAEC: An Efficient ECC With No Vacancy for Strong Memory Protection
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea
2. NVIDIA, Santa Clara, CA, USA
3. Department of Semiconductor Systems Engineering, Sungkyunkwan University, Suwon, South Korea
Funder
Institute of Information and Communications Technology Planning and Evaluation (IITP) Grant
Korean Government through the Ministry of Science and ICT (MSIT)
National Research and Development Program through the National Research Foundation of Korea
MSIT
IC Design Education Center (IDEC), South Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09866743.pdf?arnumber=9866743
Reference54 articles.
1. A New SEC-DED Error Correction Code Subclass for Adjacent MBU Tolerance in Embedded Memory
2. New SEC-DED-DAEC codes for multiple bit upsets mitigation in memory
3. Implementing triple adjacent Error Correction in double error correction Orthogonal Latin Squares Codes
4. Generating Burst-Error Correcting Codes from Orthogonal Latin Square Codes -- A Graph Theoretic Approach
5. DEC ECC design to improve memory reliability in Sub-100nm technologies
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