Reduced Resolution Redundancy: A Novel Approximate Error Mitigation Technique
Author:
Affiliation:
1. Department of Electronic Technology, Universidad Carlos III de Madrid, Leganés, Madrid, Spain
Funder
Spanish Ministry of Science and Innovation
Community of Madrid
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
General Engineering,General Materials Science,General Computer Science,Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/6287639/9668973/09715068.pdf?arnumber=9715068
Reference19 articles.
1. Reduced-Precision Redundancy on FPGAs
2. Reduced Precision Redundancy for Reliable Processing of Data
3. Partial TMR for Improving the Soft Error Reliability of SRAM-Based FPGA Designs
4. Analyzing reduced precision triple modular redundancy under proton irradiation;garcía-astudillo;IEEE Trans Nucl Sci,2022
5. Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
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4. Evaluating Reduced Resolution Redundancy for Radiation Hardening in FPGA Designs;IEEE Transactions on Nuclear Science;2023-08
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